With an understanding of Boolean Algebra, drawing the transistor level schematic is reasonably easy. In CMOS layout design, there are two sides to a device. The side that will create the logical 0 output and the side that will create the logical 1. The Boolean formula indicates one of these sides, while the other is the compliment (exact opposite).

It turns out that it is impossible to directly make an AND and an OR gate using a CMOS technique. What happens is that they automatically invert. Therefore, you can make inverted AND gates (called NAND), inverted OR gates (called NOR). and INVERTERS.

   AND |NAND       OR  |NOR
#1 #2 O|O       #1 #2 O|O
-------|-       -------|-
0  0  0|1       0  0  0|1
0  1  0|1       0  1  1|0
1  0  0|1       1  0  1|0
1  1  1|0       1  1  1|0

Notice how the NAND gate output is exactly opposite of the AND gate, and the same with the NOR relative to the OR gate. In an AND and an OR gate, when the condition is met you get a true. However for a NAND and a NOR gate, you get a false. Literally, just like adding an inverter.

In the equation for the NAND and NOR gates, the right side of the equation has a long line over it that represents the inverter. In CMOS, the only way to get an AND function is to run the output of the NAND gate into an INVERTER, thereby inverting it back. Likewise to get an OR function, a NOR's output goes into an INVERTER.

Therefore, the Boolean formula tells you exactly what the transistors look like to get the logical 0 voltage. Once the condition is met the output is a logical 0, NOT a logical 1.

There are two types of transistors used in CMOS (actually, they are called "FETs" or "Field Effect Transistors" instead of regular transistors). The FETs used on the bottom are N-FETs, while the ones on the upper half of the gate are P-FETs. They operate the same way except they need opposite voltages to turn "on." N-FETs need a logical 1 while P-FETs need a logical 0. They also have different schematic symbols.

The P-FET symbol is drawn with a little circle on the input, while the N-FET isn't. This can be used to remember that the P-FET requires a logical 0 to turn on. When the transistor is "off", legs 1 and 2 are not connected. However, once the transistor is turned on, legs 1 and 2 are connected. Therefore, CMOS FETs act almost like a switch, On/Off. With that explained, it is possible to make transistor level schematics of various logic gates.

For C to meet the condition, A AND B must be on. Note, the "condition" will make C a logical 0 instead of 1, because of the INVERTER. However, it does not change what condition must be met (only the result). This means that either one being off will violate the condition, so the bottom portion of the gate requires both A AND B.

For C to "get to" ground (logical 0), represented by the arrow head pointing down, it must pass through A AND B (series circuit).

While in an NOR gate, C can pass through either A OR B (parallel circuit). Remember that the P-FETs are configured the opposite of the N-FETs. The opposite of parallel is series and the opposite of series is naturally parallel. Therefore, the complete transistor level schematic for a NAND gate and a NOR gate are...

The long line on top represents power (logical 1). The transistor level schematic for an INVERTER is simply...