With a good transistor level schematic, the next step is to plan the layout. One of the best planing tools is the "stick diagram."

To draw a stick diagram, first draw two long horizontal lines. These will represent the P and N diffusion used to make the transistors. Next, draw a vertical line for each input. Each vertical line should cross each horizontal line. Where these lines cross represents a transistor.

Since this NAND gate has 2 inputs, there are 2 vertical lines. There is a transistor formed where a vertical and a horizontal line cross, so there are actually 4 transistors represented here (2 N-FETs and 2 P-FETs).

Now the transistor level schematic must be created.

Notice that while there are two inputs, there are a total of 4 transistors. 2 N-FETs, and 2 P-FETs. At any rate, now each vertical line must be named. They represent the input signals, and are the gate of each transistor.

Notice that the way each gate is named will affect the layout. The above is an example, and isn't the only correct way to draw the stick diagram.

Look at the transistor level schematic. For the N-FETs, transistor B has VSS on one side of it and transistor A on the other. Transistor A has B on one side and output C on the other. The stick diagram must be drawn the same way.

Notice that if VSS was in the middle of the gates, then gate A would have VSS on one side instead of gate B. Likewise, gate B would not have gate A on it's other side. Look at this stick diagram at a 90 degree angle and it looks like the transistor diagram. Not many stick diagrams resemble their transistor schematics in that way, but they do when considering what is on each side of the transistors.

Now that the N-FETs are planned out, The P-FETs must be planned out also. On one side of A is the output C and the other is VCC. Gate B is the same way, with C on one side and VCC on the other. This can be done by placing VCC between them and C on the outsides, or C in the middle and VCC on the outsides.

When a signal connects to a diffusion, it adds capacitance. This is good for power, but on signals capacitance is bad. Therefore, the "more correct" solution is to have as few connections for output C as possible.

This is the stick diagram for a 2 input NAND gate.